<jats:p>Multistage parallel interference cancellation- (MPIC-) based detectors allow to mitigate multiple-access interference in direct-sequence code-division multiple-access (DS-CDMA) systems. They are considered serious candidates for practical implementation showing a good tradeoff between performance and complexity. Better performance is obtained when decision feedback (DF) is employed. Although MPIC and DF-MPIC have the same arithmetic complexity, DF-MPIC needs much more FPGA resources when compared to MPIC without decision feedback. In this letter, FPGA implementation of block parallel DF-MPIC (BP-DF-MPIC) is proposed allowing better tradeoff between performance and FPGA area occupancy. To reach an uncoded bit-error rate of<mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msup><mml:mrow><mml:mn>10</mml:mn></mml:mrow><mml:mrow><mml:mo>−</mml:mo><mml:mn>3</mml:mn></mml:mrow></mml:msup></mml:mrow></mml:math>, BP-DF-MPIC shows a 1.5 dB improvement over the MPIC without decision feedback with only 8% increase in FPGA resources compared to 69% for DF-MPIC.</jats:p>